View DS1646_1090888.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS1646/DS1646p nonvolatile timekeeping ram DS1646/DS1646p 031698 1/12 features ? integrated nv sram, real time clock, crystal, power fail control circuit and lithium energy source ? clock registers are accessed identical to the static ram. these registers are resident in the eight top ram locations. ? totally nonvolatile with over 10 years of operation in the absence of power ? access times of 120 ns and 150 ns ? bcd coded year, month, date, day, hours, minutes, and seconds with leap year compensation valid up to 2100 ? powerfail write protection allows for 10% v cc pow- er supply tolerance ? DS1646 only (dip module) standard jedec bytewide 128k x 8 ram pin- out ? DS1646p only (powercap module board) surface mountable package for direct connec- tion to powercap containing battery and crystal replaceable battery (powercap) powerfail output pinforpin compatible with other densities of ds164xp timekeeping ram ordering information DS1646xxx 120 120 ns access 150 ns access 150 *DS1646pxxx 120 120 ns access 32pin dip module 34pin powercap module board 150 ns access 150 *ds9034pcx (powercap) required; must be ordered separately pin assignment ce oe we v cc 32pin encapsulated package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a15 nc a13 a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd oe ce we pfo v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 34 33 32 31 30 29 28 27 26 25 24 23 22 14 15 16 17 21 20 19 18 nc nc a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 nc a15 a16 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 34pin powercap module board (uses ds9034pcx powercap) x1 gnd x2 v bat pin description a0a16 address input ce chip enable oe output enable we write enable v cc +5 volts gnd ground dq0dq7 data input/output nc no connect pfo powerfail output (DS1646p only) x1, x2 crystal connection v bat battery connection
DS1646/DS1646p 031698 2/12 description the DS1646 is a 128k x 8 nonvolatile static ram with a full function real time clock (rtc) which are both ac- cessible in a bytewide format. the nonvolatile time- keeping ram is function equivalent to any jedec stan- dard 128k x 8 sram. the device can also be easily substituted in rom, eprom and eeprom sockets providing read/write nonvolatility and the addition of the real time clock function. the real time clock information resides in the eight uppermost ram locations. the rtc registers contain year, month, date, day, hours, min- utes, and seconds data in 24hour bcd format. correc- tions for the day of the month and leap year are made automatically. the rtc clock registers are double buff- ered to avoid access of incorrect data that can occur during clock update cycles. the double buffered sys- tem also prevents time loss as the timekeeping count- down continues unabated by access to time register data. the DS1646 also contains its own powerfail cir- cuitry which deselects the device when the v cc supply is in an out of tolerance condition. this feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided. packages the DS1646 is available in two packages (32pin dip module and 34pin powercap module). the 32pin dip style module integrated the crystal, lithium energy source, and silicon all in one package. the 34pin pow- ercap module board is designed with contacts for con- nection to a separate powercap (ds9034pcx) that contains the crystal and battery. this desgin allows the powercap to be mounted on top of the DS1646p after the completion of the surface mount process. mounting the powercap after the surface mount process pre- vents damage to the crystal and battery due to high tem- peratures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in seperate containers. the part number for the powercap is ds9034pcx. clock operationsreading the clock while the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a one is written into the read bit, the seventh most significant bit in the control register. as long as a one remains in that position, updating is halted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock reg- isters of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the DS1646 registers are updated simul- taneously after the clock status is reset. updating is within a second after the read bit is written to zero. block diagram DS1646 figure 1 oscillator and clock countdown chain power monitor, switching, and write protection power good clock registers 128k x 8 nvsram ce we a0a16 dq0dq7 32.768 khz + oe pfo v bat v cc
DS1646/DS1646p 031698 3/12 truth table DS1646 table 1 v cc ce oe we mode dq power 5 volts 10% v ih x x deselect highz standby 5 volts 10% x x x deselect highz standby 5 volts 10% v il x v il write data in active v il v il v ih read data out active v il v ih v ih read highz active <4.5 volts >v bat x x x deselect highz cmos standby DS1646 registers. the user can then load them with the correct day, date and time data in 24hour bcd format. resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume. stopping and starting the clock oscillator the clock oscillator may be stopped at any time. to in- crease the shelf life, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb for the seconds registers. setting it to a 1 stops the oscillator. frequency test bit bit 6 of the day byte is the frequency test bit. when the frequency test bit is set to logic a1o and the oscillator is running, the lsb of the seconds register will toggle at 512 hz. when the seconds register is being read, the dq0 line will toggle at the 512 hz frequency as long as conditions for access remain valid (i.e., ce low, oe low, and address for seconds register remain valid and stable). clock accuracy (dip module) the DS1646 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. clock accuracy (powercap module) the DS1646p and ds9034pcx are each individually tested for accuracy. once mounted together, the mod- ule is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25 c.
DS1646/DS1646p 031698 4/12 DS1646 register map bank1 table 2 address data function address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function 1ffff year 0099 1fffe x x x month 0112 1fffd x x date 0131 1fffc x ft x x x day 0107 1fffb x x hour 0023 1fffa x minutes 0059 1fff9 osc seconds 0059 1fff8 w r x x x x x x control a osc = stop bit r = read bit ft = frequency test w = write bit x = unused note: all indicated axo bits are not dedicated to any particular function and can be used as normal ram bits. retrieving data from ram or clock the DS1646 is in the read mode whenever we (write enable) is high, ce (chip enable) is low. the device ar- chitecture allows ripplethrough access to any of the address locations in the nvsram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce and oe access times and states are satisfied. if ce or oe access times are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the DS1646 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring high to low transition of we and ce . the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and re- main valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low tran- sition on we will then disable the outputs t wez after we goes active. data retention mode when v cc is within nominal limits (v cc > 4.5 volts) the DS1646 can be accessed as described above with read or write cycles. however, when v cc is below the pow- erfail point v pf (point at which write protection occurs) the internal clock registers and ram are blocked from access. this is accomplished internally by inhibiting ac- cess via the ce signal. at this time the powerfail output signal (pfo ) will be driven active low and will remain active until v cc returns to nominal levels. when v cc falls below the level of the internal battery supply, power input is switched from the v cc pin to the internal battery and clock activity, ram, and clock data are maintained from the battery until v cc is returned to nominal level.
DS1646/DS1646p 031698 5/12 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 20 c to +70 c soldering temperature 260 c for 10 seconds (see note 7) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 logic 1 voltage all inputs v ih 2.2 v cc +0.3 v logic 0 voltage all inputs v il 0.3 0.8 v dc electrical characteristics (0 c t a 70 c; v cc =5.0v 10%) parameter symbol min typ max units notes average v cc power supply current i cc1 85 ma 2, 3 ttl standby current (ce = v ih ) i cc2 3 6 ma 2, 3 cmos standby current (ce =v cc 0.2v) i cc3 2 4.0 ma 2, 3 input leakage current (any input) i il 1 +1 m a output leakage current i ol 1 +1 m a output logic 1 voltage (i out = 1.0 ma) v oh 2.4 v output logic 0 voltage (i out = +2.1 ma) v ol 0.4 v write protection voltage v pf 4.0 4.25 4.5 v
DS1646/DS1646p 031698 6/12 ac electrical characteristics (0 c to 70 c; v cc = 5.0v + 10%) parameter symbol DS1646120 DS1646150 units notes parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns output enable access time t oea 100 120 ns output enable data off time t oez 40 50 ns output enable to dq lowz t oel 5 5 ns ce to dq lowz t cel 5 5 ns output hold from address t oh 5 5 ns write cycle time t wc 120 150 ns address setup time t as 0 0 ns ce pulse width t cew 100 120 ns address hold from end of write t ah1 t ah2 5 30 5 30 ns ns 5 6 write pulse width t wew 75 90 ns we data off time t wez 40 50 ns we or ce inactive time t wr 10 10 ns data setup time t ds 85 110 ns data hold time high t dh1 t dh2 0 25 0 25 ns ns 5 6 ac test conditions input levels: 0v to 3v transition times: 5 ns capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all pins (except dq) c i 7 pf capacitance on dq pins c dq 10 pf
DS1646/DS1646p 031698 7/12 ac electrical characteristics (powerup/down timing) (0 c to 70 c) parameter symbol min typ max units notes ce or we at v ih before power down t pd 0 m s v pf (max) to v pf (min) v cc fall time t f 300 m s v pf (min) to v so v cc fall time t fb 10 m s v so to v pf (min) v cc rise time t rb 1 m s v pf (min) to v pf (max) v cc rise time t r 0 m s powerup t rec 15 25 35 ms expected data retention time (oscillator on) t dr 10 years 4 DS1646 read cycle timing t rc t rc t wc read read write t ah t as t wew valid in valid out valid out t oez t aa t oh t cea t cel t oea t oel a0a16 ce oe we dq0dq7 t wr
DS1646/DS1646p 031698 8/12 DS1646 write cycle timing t wc t wc t rc write write read a0a16 ce oe we dq0 valid out valid in valid in valid out t aa t ah1 t oea t wez t as t cew t cez t ds t dh2 t dh1 t ds dq7 t wr t wew t wr t ah2 powerdown/powerup timing v cc t pd t fb ce data retention t dr i batt t f v pf (max) v pf (min) t rec t r t rb v pf (min) v so v so pfo pfo v pf (max) v pf v pf
DS1646/DS1646p 031698 9/12 notes: 1. all voltages are referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. data retention time is at 25 c and is calculated from the date code on the device package. the date code xxyy is the year followed by the week of the year in which the device was manufactured. for exam- ple, 9225, would mean the 25th week of 1992. 5. t ah1 , t dh1 are measured from we going high. 6. t ah2 , t dh2 are measured from ce going high. output load +5 volts 100 pf d.u.t. 1.8k w 1k w 7. realtime clock modules (dip) can be successfully processed through conventional wavesoldering tech- niques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap version: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (alive bugo). b. hand soldering and touch up: do not touch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. DS1646 32pin package a 1 dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.670 38.42 1.690 38.93 0.715 18.16 0.740 18.80 0.335 8.51 0.365 9.27 0.075 1.91 0.105 0.67 0.015 0.38 0.030 0.76 0.140 3.56 0.180 4.57 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.010 0.25 0.018 0.45 0.015 0.38 0.025 0.64 c f g k d h b e j 32pin pkg
DS1646/DS1646p 031698 10/12 DS1646p dim min nom a 0.920 0.925 b 0.980 0.985 c d 0.052 0.055 e 0.048 0.050 f 0.015 0.020 g 0.025 0.027 pkg inches max 0.930 0.990 0.080 0.058 0.052 0.025 0.030 top view side view bottom view note: for the powercap version: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (alive bugo). b. hand soldering and touch up: do not touch or apply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
DS1646/DS1646p 031698 11/12 DS1646p with ds9034pcx attached dim min nom a 0.920 0.925 b 0.955 0.960 c 0.240 0.245 d 0.052 0.055 e 0.048 0.050 f 0.015 0.020 g 0.020 0.025 pkg inches max 0.930 0.965 0.250 0.058 0.052 0.025 0.030 top view side view bottom view
DS1646/DS1646p 031698 12/12 recommended powercap module land pattern pkg dim inches min nom max a 1.050 b 0.826 c 0.050 d 0.030 e 0.112 a d b c e 16 pl

▲Up To Search▲

Price & Availability of DS1646

	To Download DS1646 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .